Senior Soc Dft Design Engineer

Company:  NXP Semiconductors
Location: grenoble
Closing Date: 30/10/2024
Type: Temporary
Job Requirements / Description
Are you energetic, highly motivated and eager to learn new things? Looking for a role that will allow you to influence development, evaluation, and support of DFT solutions for products implemented in leading edge manufacturing technologies? As a DFT engineer for the MME team at NXP, you will be working on the fast paced, and leading edge for high-end SOCs targeted to Automotive and Industrial applications. The Design for Test (DFT) Design Engineer / Architect is responsible for defining and realizing and verifying Digital DFT functions on IPs, Subsystem or IC level based on required specifications.We are looking for a candidate who has solid understanding of DFT design and verification tasks who can provide efficient, high quality solutions for advanced products. For decades, we at NXP have been developing innovative microchips that can be found almost everywhere – and make life possible as we know it today. Whether it’s in credit cards, in smartphones or cars – we as a world market leader make sure that your life is easier, better and safer.Your responsibilities:Develop DFT solution for advanced products in leading edge manufacturing technologiesAlign DFT implementation with the SOC platform and IP blocks in order to deliver a cost-effective, high quality implementationDevelop DFT patterns, using ATPG, which meet product test requirements for Scan Stuck-At, Transition Delay, Memory BIST and Logic BISTParticipate in Silicon evaluation to ensure test patterns are operational immediately after silicon arrivesStay up-to-date on best design practices and industry trends for DFT which will help drive future improvementsYour profile:Master's degree in Electrical Engineering Computer Engineering or Electrical Computer Engineering.Good experience in DFT SoC developmentJTAG Boundary Scan Design & implementationScan ATPG pattern generation and retargeting, ATPG GLS with timing validationMemory BIST Algorithm development and implementationScan DRC and netlist quality debugExperience with industry standard DFT tools such as Synopsys or MentorFluent in English language both oral and written
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