Senior Physical Design Engineer (W/M)

Contract type: Permanent Starting Date: Immediately Location: Paris, Caen, Grenoble - FRANCE Offer date: 29/04/2024 Offer Ref.: scx_snr_be_des_2022_01 Job function: SCALINX’s design team is seeking a dynamic and highly motivated Physical design engineer who will participate in the design of a state-of-the-art CMOS Transceiver ASIC for the Communications market. The candidate will execute the backend process through the entire RTL-to-GDSII flow including hierarchical floor planning, place & route, timing closure, power integrity, static timing verification, physical verification, and equivalence checks, in close collaboration with the mixed-signal and digital IC design engineers. Work description: Responsible for the physical implementation from RTL to GDSII of a complex ASIC in advanced CMOS process (22nm and below technologies) Work closely with the RTL design team to understand the digital architecture and execute the physical design implementation Participate in the definition and development of the physical implementation flow Manage floorplan, pin placement, power planning, and block/top level assembly Participate in defining the supply strategy and standard cell choice Elaborate timing budget and write power intent (SDC) based on the design information and specification requirement Achieve timing and physical closure, including lithography optimizations Perform Quality Assurance checks (i.e., DRC, LVS, equivalence, power intent checking) Perform Quality of Result checks including signoff timing analysis and power analysis (IR drop, Electromigration checks, power consumption analysis) Integrate DFT scan Participate in the evaluation of the fabricated ASIC in our measurement lab Work in a team to successfully design a state-of-the-art ASIC Participate in design reviews Write documentation in accordance with company QA policy Qualification and Experience: You have a MSc or PhD in Electrical Engineering or equivalent and 10+ years of hands-on experience in physical design of digital IC from RTL to GDSII You have knowledge of scripting languages (TCL, Python, Bash, Make, Skill) A previous experience with Cadence physical design flow is mandatory Experience with the full RTL to GDS2 physical design flow execution (Synthesis, P&R, STA, DFT insertion, DRC and LVS sign-off) with 22nm and below technologies is mandatory. An experience with large designs (>1M gates) with advanced CMOS technologies (22nm and below) and high clock speed (up to 1Ghz) is a plus A previous experience in physical implementation of digital processing functions for Mixed-Signal ICs such as A/D Converters, D/A Converters, and/or RF transceivers is a plus You demonstrate good analytical and problem-solving skills You are a team player with a critical attitude and sense of initiative You communicate fluently in English (oral and written) How to apply: If you have a passion for IC design and the ambition to create something different, it will be a great pleasure to receive your resume at [email protected] SCALINX is committed to diversity & equity; we aim to improve disability inclusion within our workforce. #J-18808-Ljbffr