Senior Analog IC Design Engineer - Power management

Senior Analog IC Design Engineer - Power Management Location: Caen/Sophia-Antipolis C&S (Connectivity and Security) Analog/RF team develops combo chips for the mobile phone market, including NFC technology + Secure Element technology, Bluetooth, WiFi and Ultra-Wide Band. The key targeted markets are phone payment applications, secure transaction, gaming connectivity as well as connectivity for the Internet Of Things business. NXP is a world leader in the Secure transaction business, especially for phone payment applications. This business is constantly growing. Over this lead position, NXP connectivity chips are integrated into the most famous high-end gaming platform and still willing to extend this lead position. We are looking for an analog designer in power management to join our team. Your Responsibilities: Define key specifications, drive feasibility and design, and perform simulations of power management blocks such as regulators, bandgap, and DC-DC converters. Provide accurate estimations for silicon area. Engage during design execution to meet aggressive schedules and specifications. Offer guidance to digital and layout teams. Hands-on lab evaluation of silicon ICs. Work with verification and validation team. Implement DFT strategy to achieve competitive test time. Support test development engineers for production ramp-up. Contribute to regular peer-to-peer reviews and design reviews. Support IC leader designers with customer demands. Support the Group Leader for the planning and execution of projects and resource allocation. Support/Mentorship of junior analog design engineers. Key Performance Indicators: Take responsibility for the power management part of NFC, UWB, and BT products and drive leading-edge solutions. Meet agreed goals under pressure. Engaged, self-motivated, flexible, and enthusiastic team player. Your Profile: Passionate about analog design. Master’s degree in electronic/electrical engineering. Minimum 5-8 years hands-on experience in analog design of building blocks. Solid fundamentals of transistor level integrated circuits and device physics. Proven track record of involvement in at least one IC that has reached high volume production. Knowledge of layout matching and parasitics, latch-up, ESD, etc. Excellent analytical skills and a proactive way to work. Good communication and teamwork skills. Demonstrate innovative and creative attitude. Taking initiative to propose and implement improvements. Familiarity with EDA design tools and Cadence design environment. Knowledge in power management design and applications is desirable. #J-18808-Ljbffr